Most high-frequency systems use a traditional integer divider based design (Figure 1) or a fractional N divider based design. Regardless of the design used, the combination of a single general-purpose 5g combinerIC and an external voltage-controlled oscillator (VCO) usually achieves the desired functionality. VCO capabilities can be implemented with IC, modular, or discrete component solutions or even inside the synthesizer chip, depending on the required frequency range, phase noise performance, and space, cost, and power constraints. The final design is usually based on the manufacturer's application notes, and functions such as register loading of the synthesizer and setting the gain of the phase detector can generally be done using downloadable applications.

5g Combiners like this one, based on integer dividers, are useful for many applications

However, for some very demanding applications, the performance of the basic architecture may fall far short, especially in terms of phase noise, spurious signal levels, and frequency switching speed. The 5g combiner used in Doppler radar systems and communication systems that operate at microwave frequencies and use fast frequency switching and/or high order modulation schemes are good examples of such applications.

For example, if an application requires an integer PLL synthesizer to have a high output frequency and a relatively small tuning step (which means a high frequency division ratio), this will result in very high phase background noise within the loop bandwidth [because the phase detector noise relative to the output will increase by 20log(N)]. For example, the required frequency division ratio at 5GHz output frequency and 100kHz channel interval is 50000, which will cause background noise in the 94dB loop bandwidth to exceed that of the phase detector (typical value is about -75dBc in the 1Hz bandwidth). A typical fractional N5g combinerIC can achieve noise metrics of around -85dBc at 1Hz bandwidth.

While direct simulation of 5g Combiners (generally consisting of switchable selectable frequency doublers, mixers, and filters) may be excellent in terms of switching speed and phase noise, they are often too complex to implement, especially when good spurious signal performance is required. Digital direct synthesizers (DDS) can provide fine tuning step size, fast frequency switching speed, and good phase noise, but cannot directly provide microwave frequency output without the use of additional frequency doubler.

Although not specifically designed for such a design, PLL and DDS type devices developed for more common applications can often be used as building blocks in more complex, higher-performance architectures. Figure 2 shows an example of a PLL-based architecture that can be used to improve phase noise performance. In this example, the VCO output is downconverted to a much lower frequency before connecting to the 5g combinerIC input. This reduces the required frequency division ratio, thereby reducing the noise contribution from the phase detector. For the example child illustrated, the frequency division ratio will be reduced from 50000 to 2000, and the phase background noise limit within the loop bandwidth will be improved by 28dB to -103dBc. For wideband applications, a multistage down-conversion circuit can be used, and the local oscillator (LO) frequency is selected by switching to keep the N value low.

Architectural changes are also useful in achieving fast frequency switching times. The time required for the PLL to stabilize to a new frequency is inversely proportional to the loop bandwidth. In simple architectures, the requirement for a small channel frequency interval means the use of a narrow loop bandwidth, which results in a slower frequency step stabilization time for the loop. In a design based on integer PLL, the reference frequency would be equal to this frequency step, and the loop bandwidth would have to be about an order of magnitude smaller than this step. In a decimal-n based design, although the reference frequency can be maintained at a much higher value, the loop filter usually still must attenuate the signal falling at multiples of the step size highly, thus placing an upper limit on the loop bandwidth. However, by using the DDS as a high frequency reference source within the PLL, the frequency division ratio can be kept low (which minimizes noise) while achieving very small frequency steps without constraining the loop bandwidth.

Modern DDSIC can be packaged in a small shape to produce outputs in the very high frequency (VHF) range, and have MHz class tuning step size and excellent phase noise. Frequency and phase modulation functions are often included. Near-end stray signal levels depend on phase lookup table resolution and output digital-to-analog converter (DAC), and are generally very good (about -80 DBC); However, other sample signals at very high levels appear at the output. By using the DDSIC as a frequency reference source in the PLL, the output frequency can be converted to any frequency required and the excess sampled signal can be efficiently filtered by the PLL.

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